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DESIGNING A SOPC FOR FACE RECOGNITION USING WMPCA ALGORITHM

Nhu Thanh Truong 1, *
Diem Thi Tran 1
  1. University of Science, VNU-HCM
Correspondence to: Nhu Thanh Truong, University of Science, VNU-HCM. Email: pvphuc@hcmuns.edu.vn.
Volume & Issue: Vol. 14 No. 4 (2011) | Page No.: 24-33 | DOI: 10.32508/stdj.v14i4.2033
Published: 2011-12-30

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Copyright The Author(s) 2023. This article is published with open access by Vietnam National University, Ho Chi Minh city, Vietnam. This article is distributed under the terms of the Creative Commons Attribution License (CC-BY 4.0) which permits any use, distribution, and reproduction in any medium, provided the original author(s) and the source are credited. 

Abstract

A flexible accelerator hardware for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real-time image compression and recognition applications. Nowadays, FPGA and its SoPC (System on Programmable Chip) tools are powerful enough to efficiently develop a flexible hardware accelerator for VQ application. In addition, one of statistical analysis methods, weighted modular principal component analysis, has showed efficiencies in recognition applications. In this paper, a parallel architecture for online face recognition using weighted modular principal component analysis (WMPCA) and its system-on-programmable-chip (SoPC) implementation are discussed.

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