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IMPROVE FAULT TOLERANCE, SHORTEST PATH ROUTING IN HYPER DE BRUIJN ASTER NETWORK

Nguyen Chi Ngoc 1
Nguyen Hong Thai 1
Pham Minh Tri 1
Volume & Issue: Vol. 10 No. 13 (2007) | Page No.: 88-96 | DOI: 10.32508/stdj.v10i13.2868
Published: 2007-12-31

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This article is published with open access by Viet Nam National University, Ho Chi Minh City, Viet Nam. This article is distributed under the terms of the Creative Commons Attribution License (CC-BY 4.0) which permits any use, distribution, and reproduction in any medium, provided the original author(s) and the source are credited.

Abstract

In this article, we investigate the properties of Hyper de Bruijn Aster Networks in order to evolve the Fault Tolerance, Shortest Path Routing applying into the network of multiprocessor's application, parallel processing systems. By giving new method of routing basing on features of duplex mapping in Hyper de Bruijn Aster Network, we can achieve more possibilities in routing than other recent researches that refers to increase the performance of Fault Tolerance and Shortest Path Routing.

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