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Abstract
This work proposes a hardware architecture for HMM-based text-to-speech synthesis system (HTS). In high speed platforms, HTS with software core-engine can satisfy the requirement of real-time processing. However, in low speed platforms, software core-engine consumes long time-cost to complete the synthesis process. A co-processor was designed and integrated into HTS to accelerate the performance of system.
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Article Details
Issue: Vol 18 No 3 (2015)
Page No.: 210-217
Published: Aug 30, 2015
Section: Natural Sciences - Research article
DOI: https://doi.org/10.32508/stdj.v18i3.838
Copyright Info
Copyright: The Authors. This is an open access article distributed under the terms of the Creative Commons Attribution License CC-BY 4.0., which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
How to Cite
Su, K., Huynh, T., & Bui, T. (2015). An efficient hardware architecture for HMM-based TTS system. Science and Technology Development Journal, 18(3), 210-217. https://doi.org/https://doi.org/10.32508/stdj.v18i3.838
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