Downloads
Download data is not yet available.
Abstract
This work proposes a hardware architecture for HMM-based text-to-speech synthesis system (HTS). In high speed platforms, HTS with software core-engine can satisfy the requirement of real-time processing. However, in low speed platforms, software core-engine consumes long time-cost to complete the synthesis process. A co-processor was designed and integrated into HTS to accelerate the performance of system.
Author's Affiliation
Article Details
Issue: Vol 18 No 3 (2015)
Page No.: 210-217
Published: Aug 30, 2015
Section: Natural Sciences - Research article
DOI: https://doi.org/10.32508/stdj.v18i3.838
How to Cite
Su, K., Huynh, T., & Bui, T. (2015). An efficient hardware architecture for HMM-based TTS system. Science and Technology Development Journal, 18(3), 210-217. https://doi.org/https://doi.org/10.32508/stdj.v18i3.838
Download Citation
Article Statistics
HTML = 1076 times
Download PDF = 569 times
Total = 569 times
Download PDF = 569 times
Total = 569 times
Most read articles by the same author(s)
- Toan Van Nguyen, Dang Quoc Minh Do, Phuc Duc Nguyen, Thuan Huu Huynh, Thuc Dinh Nguyen, Designing a high performance cryptosystem for video streaming application , Science and Technology Development Journal: Vol 18 No 3 (2015)